Job Description

Job Title: Tech Lead FPGA

Job Location: Redmond & Seattle, WA (Onsite for 5 days a week)

Job Type: Contract and Fulltime

Experience: 8-15 Years (Note more than 18 years)

Job Description:

• Should have some lead experience, even hands on experience in also fine.
• Design Verification expertise in System Verilog /UVM for Unit/Module level Verification
• Should have Lead Design Verification Team ( Min 5 Members)
• Strong background in developing UVM Testbenches from scratch
• Experience in VIP Integration and Bring up
• Porting Existing Verilog/VHDL environment to UVM based Environment
• Experience in test planning ,Coverage Coding and Debugging
• Deep Knowledge of AMBA Protocol is must

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